Knowledge base
4 mins
What is RISC-V? A Revolution in Processor Architecture

In the realm of computer architecture, a new player has emerged that is set to revolutionize the industry: RISC-V.


As an open-source hardware instruction set architecture (ISA), RISC-V is changing the rules of the game, offering a level of customization and flexibility previously unseen in the processor market. This article aims to demystify RISC-V, exploring its origins, its unique features, and the potential it holds for the future of computing.

The Origins of RISC-V

RISC-V was born out of a need for a new kind of processor architecture. Traditional proprietary ISAs, such as those developed by Intel and ARM, have dominated the market for decades. However, these ISAs come with licensing fees and restrictions that limit their customization and scalability.

In contrast, RISC-V was developed by researchers at the University of California, Berkeley, with the goal of creating a free and open ISA that could be used in a wide range of applications. Launched in 2015, RISC-V is not owned by any single company, making it freely available for anyone to use, modify, and distribute.

Understanding RISC-V

RISC-V is based on the principles of Reduced Instruction Set Computing (RISC), a design philosophy that emphasizes simplicity and efficiency. Unlike Complex Instruction Set Computing (CISC) architectures, which have a large set of complex instructions, RISC architectures like RISC-V have a smaller set of simpler instructions. This simplicity allows for faster execution of instructions and more efficient use of hardware.

One of the key features of RISC-V is its modularity. The ISA is divided into modules or extensions, each of which defines a set of instructions that perform a specific function. This modular design allows for a high degree of customization, as users can choose to implement only the extensions they need, reducing the complexity and power consumption of their hardware.

The Impact of RISC-V

The impact of RISC-V on the processor market could be significant. As an open-source ISA, RISC-V has the potential to lower costs, increase innovation, and foster competition in an industry traditionally dominated by a few key players.

For hardware developers, RISC-V offers the freedom to customize their processors to meet their specific needs, without the licensing fees and restrictions associated with proprietary ISAs. For software developers, RISC-V offers a stable target for software development, as the base ISA is frozen, meaning it will not change in future versions.

The Future of RISC-V

Looking ahead, the future of RISC-V appears promising. With a growing community of developers and a wide range of applications, from microcontrollers to supercomputers, RISC-V is poised to become a major player in the processor market.

However, like any new technology, RISC-V faces challenges. These include the need for a robust ecosystem of tools and software, the need for standardization among different RISC-V implementations, and the need to convince hardware manufacturers to adopt a new ISA.

Despite these challenges, the potential benefits of RISC-V - lower costs, increased customization, and open development - make it a compelling option for the future of processor design.

CKB-VM: The RISC-V-based Blockchain Virtual Machine

One of the most exciting applications of RISC-V is in the world of blockchain technology. A prime example of this is the Nervos Network, a multi-layered blockchain ecosystem. At the heart of Nervos is its Layer 1 protocol, the Common Knowledge Base (CKB). CKB utilizes RISC-V in its virtual machine, the CKB-VM.

The CKB-VM is a key component of the Nervos Network. It's responsible for verifying the correctness of smart contract interactions and transaction scripts, essentially serving as the "brain" of the CKB. By using RISC-V, the CKB-VM can leverage the simplicity, efficiency, and modularity of the RISC-V architecture.

The use of RISC-V in the CKB-VM offers several benefits. First, it allows for greater flexibility in smart contract execution. Developers can write smart contracts in any programming language, as long as they can be compiled to RISC-V instructions. This opens up a world of possibilities for smart contract development. With CKB, developers are not limited to a single language.

Second, the use of RISC-V ensures that the CKB-VM is future-proof. As an open standard, RISC-V is continually being developed and improved by a global community of researchers and engineers. Any improvements to the RISC-V architecture can be incorporated into the CKB-VM as extensions, ensuring that it remains at the cutting edge of technology.

Finally, the use of RISC-V contributes to the security and stability of the CKB. The RISC-V architecture has been extensively tested and verified, and its simplicity reduces the risk of bugs and vulnerabilities. Because of RISC-V’s modularity, upgrades are built on top of the frozen “core” instruction set, and CKB can be elegantly upgraded through using extensions.


In conclusion, RISC-V represents a significant shift in the world of processor architecture. As an open-source ISA, it offers a level of freedom and flexibility that is unprecedented in the industry.

While it faces challenges in terms of adoption and ecosystem development, its potential benefits make it a compelling option for hardware and software developers alike. As the RISC-V community continues to grow and evolve, it will be exciting to see how this innovative ISA shapes the future of computing.